
BĆ1
Appendix B
Module Block Diagram
ADDRESS
DECODE
WATCHDOG
TIMER
LED
DISPLAY
2 ROTARY
SWITCHES
MULTIBUS
EXCHANGE
LOGIC
DUAL PORT
ARBITRATION
LOGIC AND
CONTROL
68010
CPU
CHIP
DUALĆPORT
MEMORY
(16KĆBYTES)
16KĆBYTE
PROM
16KĆBYTE
RAM
8257 DMA
CONTROLLER
8274 SERIAL
INTERFACE
CONTROL
LOGIC
AND
BUFFERS
ISOLATION
CIRCUITS
CONDITIONĆ
ING
ISOLATED
DĆC/DĆC
CONVERTER
+12VI
0VI
-12VI
+5 VOLTS
+12 VOLTS
- 12 VOLTS
GROUND
ADDRESS
I/D
BUS
ADĆ
DRESS
BUS
DATA
BUS
ADDRESS AND
CONTROL BUS
ADDRESS BUS
CTRL BUS
DATA
BUS
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